Function report |
Source Code:include\linux\irq.h |
Create Date:2022-07-28 07:33:00 |
Last Modify:2020-03-12 14:18:49 | Copyright©Brick |
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Annotation kernel can get tool activity | Download SCCT | Chinese |
Name:irq_reg_writel
Proto:static inline void irq_reg_writel(struct irq_chip_generic *gc, unsigned int val, int reg_offset)
Type:void
Parameter:
Type | Parameter | Name |
---|---|---|
struct irq_chip_generic * | gc | |
unsigned int | val | |
int | reg_offset |
1169 | If reg_writel Then reg_writel(val, reg_base + reg_offset) |
1171 | Else writel(val, reg_base + reg_offset) |
Name | Describe |
---|---|
irq_gc_mask_disable_reg | q_gc_mask_disable_reg - Mask chip via disable register*@d: irq_data* Chip has separate enable/disable registers instead of a single mask* register. |
irq_gc_mask_set_bit | q_gc_mask_set_bit - Mask chip via setting bit in mask register*@d: irq_data* Chip has a single mask register. Values of this register are cached* and protected by gc->lock |
irq_gc_mask_clr_bit | q_gc_mask_clr_bit - Mask chip via clearing bit in mask register*@d: irq_data* Chip has a single mask register. Values of this register are cached* and protected by gc->lock |
irq_gc_unmask_enable_reg | q_gc_unmask_enable_reg - Unmask chip via enable register*@d: irq_data* Chip has separate enable/disable registers instead of a single mask* register. |
irq_gc_ack_set_bit | q_gc_ack_set_bit - Ack pending interrupt via setting bit*@d: irq_data |
irq_gc_ack_clr_bit | q_gc_ack_clr_bit - Ack pending interrupt via clearing bit*@d: irq_data |
irq_gc_mask_disable_and_ack_set | q_gc_mask_disable_and_ack_set - Mask and ack pending interrupt*@d: irq_data* This generic implementation of the irq_mask_ack method is for chips* with separate enable/disable registers instead of a single mask* register and where a pending interrupt is |
irq_gc_eoi | q_gc_eoi - EOI interrupt*@d: irq_data |
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