Function report |
Source Code:arch\x86\kernel\cpu\mce\amd.c |
Create Date:2022-07-28 08:03:12 |
Last Modify:2020-03-12 14:18:49 | Copyright©Brick |
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Annotation kernel can get tool activity | Download SCCT | Chinese |
Name:deferred_error_interrupt_enable
Proto:static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
Type:void
Parameter:
Type | Parameter | Name |
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struct cpuinfo_x86 * | c |
455 | def_offset = -1 |
457 | If dmsr with exception handling (Deferred error settings , & low, & high) Then Return |
460 | def_new = (low & MASK_DEF_LVTOFF) >> 4 |
461 | If Not (low & MASK_DEF_LVTOFF) Then |
462 | pr_err(FW_BUG* Add this to a message where you are sure the firmware is buggy or behaves* really stupid or out of spec"Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n") |
463 | def_new = DEF_LVT_OFF |
464 | low = low & ~MASK_DEF_LVTOFF | DEF_LVT_OFF << 4 |
468 | If def_offset == def_new && deferred_error_int_vector != amd_deferred_error_interrupt Then deferred_error_int_vector = amd_deferred_error_interrupt |
472 | If Not * Indicates that overflow conditions are not fatal, when set. Then low = low & ~MASK_DEF_INT_TYPE | DEF_INT_TYPE_APIC |
475 | wrmsr(Deferred error settings , low, high) |
Name | Describe |
---|---|
mce_amd_feature_init | pu init entry point, called from mce.c with preempt off |
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