Function report |
Source Code:arch\x86\kernel\apic\apic.c |
Create Date:2022-07-28 08:26:39 |
Last Modify:2020-03-16 21:21:31 | Copyright©Brick |
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Name:If mask=1, the LVT entry does not generate interrupts while mask=0* enables the vector. See also the BKDGs. Must be called with* preemption disabled.
Proto:int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
Type:int
Parameter:
Type | Parameter | Name |
---|---|---|
u8 | offset | |
u8 | vector | |
u8 | msg_type | |
u8 | mask |
433 | reg = APIC_EILVTn(offset) |
438 | reserved = reserve_eilvt_offset(offset, new) |
441 | pr_err(FW_BUG* Add this to a message where you are sure the firmware is buggy or behaves* really stupid or out of spec"cpu %d, try to use APIC%lX (LVT offset %d) for vector 0x%x, but the register is already in use for vector 0x%x on another cpu\n", smp_processor_id(), reg, offset, new, reserved) |
445 | Return -EINVAL |
448 | If Not eilvt_entry_is_changeable(old, new) Then |
449 | pr_err(FW_BUG* Add this to a message where you are sure the firmware is buggy or behaves* really stupid or out of spec"cpu %d, try to use APIC%lX (LVT offset %d) for vector 0x%x, but the register is already in use for vector 0x%x on this cpu\n", smp_processor_id(), reg, offset, new, old) |
453 | Return -EBUSY |
456 | apic_write(reg, new) |
458 | Return 0 |
Name | Describe |
---|---|
setup_APIC_mce_threshold | |
setup_APIC_deferred_error |
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