函数逻辑报告 |
Source Code:arch\x86\include\asm\apic.h |
Create Date:2022-07-27 08:27:23 |
Last Modify:2020-03-12 14:18:49 | Copyright©Brick |
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函数名称:apic_read
函数原型:static inline unsigned int apic_read(unsigned int reg)
返回类型:unsigned int
参数:
类型 | 参数 | 名称 |
---|---|---|
unsigned int | reg |
435 | 返回:0 |
名称 | 描述 |
---|---|
mcheck_intel_therm_init | |
__inquire_remote_apic | |
wakeup_secondary_cpu_via_nmi | Poke the other CPU in the eye via NMI to wake it up. Remember that the normal* INIT, INIT, STARTUP sequence will reset the chip hard for us, and this* won't ... remember to clear down the APIC, etc later. |
wakeup_secondary_cpu_via_init | |
do_boot_cpu | NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad* (ie clustered apic addressing mode), this is a LOGICAL apic ID.* Returns zero if CPU booted OK, else error code from* ->wakeup_secondary_cpu. |
smp_get_logical_apicid | |
lapic_get_version | Get the LAPIC version |
native_apic_wait_icr_idle | |
native_safe_apic_wait_icr_idle | |
native_apic_icr_read | |
lapic_get_maxlvt | lapic_get_maxlvt - get the maximum number of local vector table entries |
__setup_APIC_LVTT | This function sets up the local APIC timer, with a timeout of* 'clocks' APIC bus clock. During calibration we actually call* this function twice on the boot CPU, once with a bogus timeout* value, second time for real. The other (noncalibrating) CPUs |
setup_APIC_eilvt | If mask=1, the LVT entry does not generate interrupts while mask=0* enables the vector. See also the BKDGs. Must be called with* preemption disabled. |
lapic_timer_shutdown | |
lapic_cal_handler | Temporary interrupt handler and polled calibration function. |
clear_local_APIC | lear_local_APIC - shutdown the local APIC* This is called, when a CPU is disabled and before rebooting, so the state of* the local APIC has no dangling leftovers. Also used to cleanout any BIOS* leftovers during boot. |
apic_soft_disable | apic_soft_disable - Clears and software disables the local APIC on hotplug* Contrary to disable_local_APIC() this does not touch the enable bit in* MSR_IA32_APICBASE |
init_bsp_APIC | An initial setup of the virtual wire mode. |
lapic_setup_esr | |
apic_check_and_ack | |
setup_local_APIC | setup_local_APIC - setup the local APIC* Used to setup local APIC while initializing BSP or bringing up APs.* Always called with preemption disabled. |
end_local_APIC_setup | |
init_apic_mappings | _apic_mappings - initialize APIC mappings |
register_lapic_address | |
smp_spurious_interrupt | This interrupt should _never_ happen with our APIC/SMP architecture |
smp_error_interrupt | This interrupt should never happen with our APIC/SMP architecture |
disconnect_bsp_APIC | disconnect_bsp_APIC - detach the APIC from the interrupt system*@virt_wire_setup: indicates, whether virtual wire mode is selected* Virtual wire mode is necessary to deliver legacy interrupts even when the* APIC is disabled. |
print_APIC_field | |
print_local_APIC | |
ioapic_ack_level | |
mask_lapic_irq | The local APIC irq-chip implementation: |
unmask_lapic_irq | |
uv_read_apic_id | |
init_x2apic_ldr | |
flat_init_apic_ldr | Set up the logical destination ID.* Intel recommends to set DFR, LDR and TPR before enabling* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel* document number 292116). So here it goes... |
read_xapic_id | |
default_init_apic_ldr | Set up the logical destination ID. Intel recommends to set DFR, LDR and* TPR before enabling an APIC. See e.g. "AP-388 82489DX User's Manual"* (Intel document number 292116). |
lapic_vector_set_in_irr | |
default_get_apic_id |
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